1. Field of the Invention
This invention relates to an integrated circuit tester to execute functional tests of integrated circuits. More particulary, it relates to an integrated circuit tester in which fail observations in the evaluation, for example, of maximum operating frequencies can be carried out effectively.
2. Description of the Prior Art
Recently, the input-output timing relation in an integrated circuit (e.g., a microprocessor) has become complicated due to the increase of input-output pins and the high function and high integration of intergrated circuits. As a result, the test method of an integrated circuit has become complicated and large scaled. From the view point of designing, a scan path method and an incorporated test method have been developed to cope with the problem mentioned above, and to simplify the test method. On the other hand, from the view point of test method, the development of an integrated circuit tester (referred as LSI tester, below) has not followed the high function and high integration:of LSIs, thus causing difficulties for developing and producing LSIs.
An example of the prior art LSI tester mentioned above is shown in FIG. 1. This LSI tester is comprised of the following: an input part (e.g., keyboard) 51, through which test pattern names required to execute tests, test conditions, such as supply voltages and test periods, are input; a control part 53, which indicates driver patterns (high level output, low level output), comparator patterns (high level comparing signal, low level comparing signal), test priods, set-up hold positions, and strobe positions for each clock, to a driver 55 and a comparator 57 (which will be mentioned below); the driver 55 which outputs driver patterns to a device under test 61 (referred as DUT below) according to the instruction by control part 53; the comparator 57 which compares a comparator pattern with the output from DUT 61 according to the instruction by control part 53; and a display 59 which indicates test results.
The basic operation of the LSI tester will be explained below.
Assume that DUT 61 has a scan function, and outputs informations contained in flip-flops and registers when particular pins are activated. In this case, test conditions are input through input part 51 first. Having recieved the test conditions, control part 53 gives instructions to driver 55 so that a test pattern is applied on DUT 61, and then, gives instruction to comparator 57 so that the output from DUT 61 is compared with an expected value. The compared result is, then, indicated on display 59.
Among the various tests which are executed during the development of an LSI, there is a test about the evaluation of maximum operating frequencies. This evaluation is carried out in the following way. The first fail clock, which has the biggest influence the operating frequency, is checked first. The reason why the operating speed is slow in that clock is due to a particular circuit which is operated under that clock. Therefore, an investigation into the cause of the first fail is conducted next, to find if there are any defects in designing. Once any defects are found, these should be repaired in the particular circuit.
In reality, when the test is executed using a particular driver pattern of one clock contained in the test patterns shown in FIG. 2, and when the output from DUT 61, operated with the lowest operating frequency, does not coincide with a comparator pattern, i.e., an expected value, then, that clock is called the first fail clock. And, the clock, in which a fail occurs with the next lower operating frequency, is called the second fail clock.
The procedure to measure maximum operating frequencies using the LSI tester shown in FIG. 1 will be explained next by referring to FIG. 3.
First, an initial value (e.g., 1 MHz) of the operating frequency is set in step 151, and a test pattern is executed in step 153. Next, whether the test pattern has passed or failed, is Judged in step 155. If the test pattern has passed, it means that the operating frequency has not reached to the maximum value. Therefore, the frequency is advanced (e.g., by 1 MHz) in step 157, in order to execute the test pattern again in step 153. In the case where the test pattern has failed in that frequency, it means that the frequency is above the maximum operating frequency. Therefore, if it is the first fail, the executed result is output as the first fail in step 159. Next, in step 161, the operating frequency is examined if it is the predetermined maximum value or not. In the case where the frequency coincides with the predetermined value, the procedure goes to the end. On the other hand, if it has not reached the predetermined value, the operating frequency is advanced in step 157 and the procedure returns to step 153 to check the next fail existence.
According to the procedure mentioned above, it is possible to find the first fail clock. However, the next fail clock, i.e., the second fail clock sometimes cannot be observed because it is overlapped or masked by the first fail clock. For example, when a first fail occurs at the 8th clock of the operating frequency 5 MHz in the test pattern shown in FIG. 2, the second fail existing between the first clock and the 7th clock can be observed. On the contrary, when a second fail exists between the 8th clock and the 16th clock, it cannot be observed. This is because the second fail is overlapped or masked by the first fail. (In those cases, the second fail is hidden by the first fail which has occurred first by the first fail clock, even if the operating frequency is so advanced.)
A concrete example of the measurement of maximum operating frequencies will be .explained below using a microprocessor which contains an adder (a circuit to execute an addition), a shifter (a circuit to execute a shift), and a multiplier (a circuit to execute a multiplication) as circuit blocks. To inspect such a microprocessor, usually, machine word instructions such as ADD instructions for an adder, SHF instructions for a shifter, and MUL instructions for a multiplier, are input from external. In general, the maximum operating frequency of each circuit block varies for each other so that these are assumed as 13 MHz for an adder, 12 MHz for a shifter, and 11 MHz for a multiplier here by way of explanation. (In fact, those are found as a result of measurements.)
In order to measure the maximum operating frequency of this microprocessor, the following 6 patterns can be expected as the test patterns.
______________________________________ a) first clock ADD instruction second clock SHF instruction third clock MUL instruction b) first clock ADD instruction second clock MUL instruction third clock SHF instruction c) first clock SHF instruction second clock ADD instruction third clock MUL instruction d) first clock SHF instruction second clock MUL instruction third clock ADD instruction e) first clock MUL instruction second clock ADD instruction third clock SHF instruction f) first clock MUL instruction second clock SHF instruction third clock ADD instruction ______________________________________
Using the LSI tester shown in FIG. 1, the microprocessor is tested according to the test patterns a) to f). When the microprocessor was operated with 11 MHz, all test patterns passed. When the microprocessor was operated with 12 MHz, it failed at the clock of MUL instructions in each test pattern, thus finding the first fail. When the microprocessor was operated with 13 MHz, it failed at the clock of SHF instructions in test patterns a), c), and d), thus finding the second fail. In other test patterns, however, the microprocessor could not find the second fail because these had been masked by the first fail. Furthermore, when the microprocessor is operated with 14 MHz, it failed at the clock of ADD instructions in test patterns a) and b) to find third fails. In test pattern c), however, this third fail could not be found because it is masked by the second fail. Also, in test patterns d), e), and f), the third fail could not be found because it is masked by the first fail. In short, all fails can be observed by test pattern a), and the maximum operating frequencies can be measured for all circuit blocks. On the other hand, only some fails can be observed by other test patterns, and the maximum frequencies of circuit blocks corresponding to these fails can be measured. In usual, there are n factorial patterns combinations in a test pattern having n clocks. So that, it is very difficult to make an ideal test pattern, i.e., test pattern a), in the measurement of maximum operating frequencies.
As described above, according to the prior art LSI tester, the fail, which occurs by the (n+1)th lower operating frequency, cannot always be observed because it is masked or overlapped by the fails occured by the nth lower operating frequency or less. As a result, defects contained in DUTs cannot always be found by the prior art LSI testers.